1. Field of the Invention
The present invention at least relates to an information processing equipment. The present invention particularly relates to an information processing equipment that includes a plurality of processors.
2. Description of Related Art
An information processing equipment such as a mainframe, a server and the like is required to perform complex processing in large amounts with high speed. For this reason, the information processing equipment is provided with dedicated processors for every function and the dedicated processors perform respective processing (For example, see Japanese Laid-Open Patent Application JP-A-Heisei. 3-63869, Japanese Laid-Open Patent Application JP-P2003-162514). The dedicated processors are exemplified by an input-output processor that controls input and output with respect to a peripheral device, an encryption processor that dedicatedly performs data encryption and decryption, a TCP/IP offload engine that dedicatedly deals with TCP/IP protocol, and the like. Such the dedicated processors are LSIs and fixedly installed in the information processing equipment.
Such the information processing equipment has the following problems. That is, when load on a certain dedicated processor is increased and hence processing power of the dedicated processor becomes insufficient, the entire performance of the information processing equipment is reduced. Also, if an only one dedicated processor installed in the information processing equipment fails, the entire information processing equipment halts. Moreover, the dedicated processor is an expensive LSI and bug fix and function addition are not easy. Therefore, a technique is desired which can freely switch the function of each processor during operations of the information processing equipment.
Japanese Laid Open Patent Application JP-A-Showa 60-252977 (hereinafter referred to as a patent document) discloses a multiprocessor system that has a plurality of processor means with different architectures. Each of the processor means has an input-output processor function in addition to its primary processor function. The each processor means is so configured as to perform the input-output processor function during its idle state in accordance with an instruction from a bus-dominance control means.
According to the technique disclosed in the patent document, the processor means having its primary processor function can be switched during the idle state to perform the input-output processor function. However, for example, the processor means can not perform a new function which the processor means does not originally have (in the case of the patent document, the new function is a function other than the primary processor function and the input-output processor function). There may be a case where a processor function needs to be switched to a function that the processor does not originally have, while the processor function can not freely be switched depending on the situation. For example, if an only one dedicated processor installed in the information processing equipment fails and the function of that one dedicated processor is a function which the other processors do not originally have, the operations of the entire information processing equipment stop.